In order to support the 1-wire device bus on an embedded system, by far the most typical implementation is in a micro controller bit-banging an open drain output with a pull-up. Unfortunately, this methodology is impossible to do reliably in Linux. 1-wire works by precisely timing output pulses; a logic '1' is transmitted as a 6us low pulse and a logic '0' is nominally 60us. We already know from this thread: that at this timescale Linux does not behave like a RTOS and if the CPU services a ethernet or timer interrupt in the middle of bit-banging out the pulse a logic 1 could be turned into a logic 0 or you could miss RX bits from the device.

To accommodate this, TS has written a Verilog FPGA core that can be inserted into any of our boards with a customizable FPGA. As consistent with all TS FPGAs, this core is a WISHBONE slave peripheral implemented in the simplest, most direct way that minimizes logic resource usage and design complexity. Indeed, there are other 1-wire FPGA cores out there but they have much more complicated implementations, software interfaces, and resource utilization. The TS core is approximately 130 LUTs and ~211 lines of Verilog which is about 2.5% of the size of the typical FPGA on the TS-75xx product line. Additionally, it supports 8 simultaneous 1-wire busses.

The source code of this core is attached below. Customers of TS using a TS supplied FPGA or CPU base board can freely use, modify, and otherwise instantiate this core in their custom FPGAs however they see fit. It is NOT licensed with the GPL or other such open source license that requires modifications to be re-submitted openly. TS doesn't care what you do with the source as long as its used only with our products and the GPL or LGPL license is frankly too restrictive.

Documentation is included in the source comments, but also listed here:


/* Core for Dallas/Maxim 1-wire buses.  A good tutorial on one-wire is
 * here:
 * This core contains only 1 16-bit register and works by doing 1-wire
 * read/write ops 8-bits at a time.  Only master mode is supported--
 * this core cannot act as a 1-wire device.
 * This core follows recommended timing from diagrams for standard speed at:
 *  Overdrive mode is
 * not supported.
 * Register map:
 * base + 0x0:
 *   bits 15-13: 1-wire LUN select (0-7) (RW)
 *   bit 12: busy (RO), special cmd enable (WO)
 *   bit 11-8: bytes to read (RW)
 *     0x0 - read disabled
 *     0x1 - read 1 byte
 *     0x2 - read 2 bytes
 *     ...
 *     0xd - read 13 bytes
 *     0xe - read 1 bit (returns read bit in bit 7)
 *     0xf - read 2 bits (returns first read bit in bit 6, 2nd in bit 7)
 *   bit 7-0: read/write data or special cmd opcode
 * * The "bytes to read" reg will auto-decrement after each read.  A simple
 *   1-wire message involving 4 bytes (e.g. 2 writes followed by 2 reads) will
 *   take precisely 4 bus cycles.  A 1-wire write will not happen on WB write
 *   while the "bytes to read" reg is non-zero.  
 * * The "bytes to read" reg can be updated without also initiating a
 *   1-wire byte write by writing with the "special cmd" bit set.
 * * When "special cmd" bit 12 is set, bits 7-0 have special meaning:
 *     8'b0000_0000 - no special cmd, no-op.
 *     8'b1xxx_xxxx - initiate 1-wire reset, presence returned in bit 0,
 *                    short detect return in bit 1
 *     8'b01xx_xxxx - 1-bit write, bit written is bit 0
 * Whether or not read bus cycles "block" can be affected by enabling the
 * "read_block_enable_opt" Verilog compile-time parameter.  When enabled, a
 * WB read will be held off while bits are shifted in.  When disabled,
 * WB reads complete immediately but software has to watch the
 * "bytes to read" reg decrement to know if new RX data is available.  WB write
 * cycles MAY block if the core is currently busy transmitting the previous
 * byte-- blocking may be avoided here by polling for bit 12 to be 0 before
 * initiating another back to back write.  
 * After tristating the 1-wire bus during a read, the core can actively "push"
 * the state of the line to a hard 1 for 2us after the slow pull-up reaches the
 * digital logic threshold voltage.  This helps recharge the parasite power cap
 * on the 1-wire devices during a read and is what the DS2482 I2C 1-wire master
 * does by default.  This behavior can be turned on or off with
 * the "push_1_opt" synthesis parameter.  

Some useful 1-wire links:

1-Wire Online Tutorial

1-wire timing diagrams

Wikipedia page on 1-wire

Maxim's 1-wire iButton devices